Decomposed floating point multiplication

ABSTRACT

Systems, apparatuses and methods may provide for technology that in response to an identification that one or more hardware units are to execute on a first type of data format, decomposes a first original floating point number to a plurality of first segmented floating point numbers that are to be equivalent to the first original floating point number. The technology may further in response to the identification, decompose a second original floating point number to a plurality of second segmented floating point numbers that are to be equivalent to the second original floating point number. The technology may further execute a multiplication operation on the first and second segmented floating point numbers to multiply the first segmented floating point numbers with the second segmented floating point numbers.

TECHNICAL FIELD

Embodiments generally relate to operations related to multiplicationtechnology. More particularly, embodiments relate to decomposingfloating point numbers to execute multiplication (e.g., matrixmultiplication) on existing hardware.

BACKGROUND

Many compute cycles in certain workloads (e.g., deep learning workloadand/or neural network learning) may be spent performing matrixmultiplications that consume data in some input type and produce aresult in a possibly different output type. For example, deep learningworkload and/or neural network learning may execute matrixmultiplication to determine weights.

Because of area constraints, some hardware multiplication units mayconsume only a first type of data (e.g., brain floating point 16 format)as an input, while producing an output that is either the first type ofdata or a second type of data (e.g., float 32 format). The second typeof data may be more precise than the first type of data. In some cases,the input is insufficient to generate a useful output due to the lowerprecision of the first type of data. To increase precision, the matrixmultiplication may need to be adjusted to consume the second type ofdata as an input instead of the first type of data.

BRIEF DESCRIPTION OF THE DRAWINGS

The various advantages of the embodiments will become apparent to oneskilled in the art by reading the following specification and appendedclaims, and by referencing the following drawings, in which:

FIG. 1 is an example of a process to decompose numbers to a differentdata format according to an embodiment;

FIG. 2 is a flowchart of an example of a method of executingmultiplication according to an embodiment;

FIGS. 3A-3C are an example of a process of executing matrixmultiplication according to an embodiment;

FIG. 4 is a flowchart of an example of a method of adjusting agranularity of matrix multiplication operations according to anembodiment;

FIG. 5 is an example of a process of number decomposition according toan embodiment;

FIG. 6 is a block diagram of an example of a computing system accordingto an embodiment;

FIG. 7 is an illustration of an example of a semiconductor apparatusaccording to an embodiment;

FIG. 8 is a block diagram of an example of a processor according to anembodiment; and

FIG. 9 is a block diagram of an example of a multi-processor basedcomputing system according to an embodiment.

DESCRIPTION OF EMBODIMENTS

FIG. 1 illustrates a process 10 to decompose first and second numbers12, 26 to a different data format to execute multiplication. In detail,process 10 may utilize existing hardware, which executes on a first typeof data format, to process first and second numbers 12, 26 that are in asecond data format. For example, the first type of data format may bebrain floating point 16 (bfloat16) format and the second type of dataformat may be in a single-precision floating-point format (float32).Process 10 may therefore utilize existing hardware (e.g., a bfloat-onlypipeline) to process data (e.g., float32) that would otherwise beincompatible with the existing hardware. As discussed in further detailbelow, a granularity of the process 10 may also be adjusted to balanceperformance of the hardware against the accuracy of the output.

In the example of FIG. 1, the first number 12 and the second number 26may be in the second format. In detail, the first number 12 and thesecond number 26 may each have a sign bit (e.g., indicates positive ornegative), exponent bits (e.g., indicates an exponent and/or a biasedexponent) and mantissa bits (e.g., a significand or fraction). Aplurality of numbers 16, 18, 20, 28, 30, 32 of the first type of dataformat may represent the first and second numbers 12, 26. For example,if the first and second numbers 12, 26 are each originally in float32format, the first and second numbers 12, 26 may each be represented by asum of three bfloat16 16, 18, 20, 28, 30, 32 components with little tono information loss.

As illustrated, the first and second numbers 12, 26 may be decomposedinto smaller components 14. In detail, the first high number 16, thefirst medium number 18 and the first low number 20 may be in the firsttype of data format to represent the first number 12.

The first high number 16 may include the most significant mantissa bitsof first number 12. For example, the first high number 16 may include anexponent, the sign of the first number 12 and the first N-bits (e.g.,the implicit bit and bit positions 22-16 and/or 8 bits total) of themantissa of the first number 12. The exponent of the high number 16 maybe identical to the exponent of the first number 12.

The medium number 18 may include an exponent, a sign associated withnext most significant N-bits of the mantissa (e.g., signs may differ dueto rounding to nearest mode used during extraction of the 3 bfloatnumbers) and the next most significant N-bits of the mantissa (e.g.,ranging from bit positions 15-8 and/or 8 bits total) of the mantissa ofthe first number 12. Thus, in some embodiments the sign of the mediumnumber 18 may be different from the sign of the first number 12depending on the value in the next most significant N-bits. The exponentof the medium number 18 may be determined from the exponent of the firstnumber 12. For example, the exponent of the first number 12 may bereduced to reflect the lower bit positions of the mantissa of the firstnumber 12 that are to be stored in the medium number 18. The reducedexponent may be stored as the exponent of the medium number 18. Forexample, the exponent of the first number 12 may be reduced by an amount“X” (e.g., 8) and stored as the exponent of the medium number 18.

The low number 20 may include an exponent, a sign associated with theremainder of the mantissa, and the remainder of the mantissa (e.g.,ranging from bit positions 7-0 and/or 8 bits total) of the mantissa ofthe first number 12. In some embodiments the sign of the low number 20may be different from the sign of the first number 12 depending on thevalue in the remainder of the mantissa. The exponent of the low number20 may be determined from the exponent of the first number 12. Forexample, the exponent of the first number 12 may be reduced to reflectthe lowest bit positions of the mantissa of the first number 12 that areto be stored in the low number 20. The reduced exponent may be stored asthe exponent of the first number 12. For example, the exponent of thefirst number 12 may be reduced by an amount “2X” (e.g., 16) and storedas the exponent of the low number 20. As noted, the exponent of the lownumber 20 may be smaller than the exponent of the medium number 18, andthe exponent of the medium number may be smaller than the exponent ofthe high number 16.

Likewise, the second high number 28, the second medium number 30 and thesecond low number 32 may be in the first type of data format torepresent the second number 26. The exponent of the second number 26 mayalso be adjusted as described above to generate the second high number28, the second medium number 30 and the second low number 32.

In some embodiments, to convert the first number 12 and the secondnumber 26 each into three components that are in the first type of dataformat, different algorithms may be used. For example, to convert afloat32 variable a into three bfloat components the following algorithmmay be used to split variable a into high component a_(h), mediumcomponent a_(m) and low component a_(t): 1) a_(h)=(bfloat)a;define(t)=a−a_(h); 2) a_(m)=(bfloat)t; t=t−a_(m); 3) a_(l)=(bfloat)t.The expected exponents of high, medium and low components a_(h), a_(m),and a_(l) are generated as follows: 1) a_(h) has the same exponent as a;2) a_(m) has an exponent that is at least 8 lower than a; 3) a_(l) hasan exponent that is at least 16 lower than a. A “(bfloat)a” operationmay be a cast operation which down-converts from fp32 to bfloat. Thus,in this example, high component a_(h) contains the sign, the abovedetermined exponent and the most significant 8 bits of the mantissa ofthe variable a. Medium component a_(m) stores the sign, the abovedetermined exponent and the next 8 bits of the mantissa of variable athat start after the mantissa bits stored by high component a_(h). Thelow component a_(l) stores the sign, the above determined exponent andthe remainder of the mantissa of number a that are not stored by eitherof high component a_(h) or medium component a_(m). In some embodiments,the value of high component a_(h) alone may be used to approximate thevalue of variable a. The value of high component a_(h)+medium componenta_(m) may more precisely represent the value of variable a, and value ofhigh component a_(h)+medium component a_(m)+low component a_(l) isprecisely equal to the value of variable a.

Process 10 may then execute a multiplication operation 22. For example,multiplication of the first and second numbers 12, 26 (that may be inthe second type of data format) may correspond to multiplications thatconsumes the first high number 16, the first medium number 18, the firstlow number 20, the second high number 28, the second medium number 30and the second low number 32 that are each in the first type of dataformat. The result of the multiplication may be in the second type ofdata format. The multiplication operation 22 may be a matrixmultiplication operation.

For example, if the first and second numbers 12, 26 are originally infloat32 format, a multiplication operation may be executed on bfloat16numbers, such as first and second low-high numbers 16, 18, 20, 28, 30,32, to produce a result that is an output number in float32 format. Forexample, a single matrix in the second type of data format (e.g.,float32 numbers) may be represented by three or more matrices in thefirst type of data format (e.g., in bfloat16) that may be addedelement-wise together to reconstruct the original matrix. Therefore,matrix multiplication of two matrices in the second type of data formatmay be expressed as sequence of matrix multiplications that consume onlymatrices in the first type of data format to produce a matrix output inthe second type of data format. The matrix multiplication may befollowed by element-wise addition.

For example, multiplication of the first number 10 and the second number26 may be represented by:

(the first low number 20*the second low number 32)+(the first low number20*the second medium number 30+the first medium number 18*the second lownumber 32)+(the first low number 20*the second high number 28+the firstmedium number 18*the second medium number 30+the first high number16*the second low number 32)+(the first medium number 18*the second highnumber 28+the first high number 16*the second medium number 30)+(thefirst high number 16*the second high number 28)  EQUATION I

As illustrated, the first high number 16, the first medium number 18,the first low number 20, the second high number 28, the second mediumnumber 30 and the second low number 32 may be multiplied together togenerate a final output. Furthermore, the various operations above mayhave different exponential values because of the different exponentialvalues of the first high number 16, the first medium number 18, thefirst low number 20, the second high number 28, the second medium number30 and the second low number 32. For example, Table I below illustratesthe various exponential values of the operations above:

TABLE I Medium Medium High High Medium Low Low Exponent ExponentExponent Exponent Exponent Operation the first high the first the firsthigh number 16 * medium number 16 * the second number 18 * the secondhigh number 28 the second low number 32 high number 28 Operation thefirst high the first the first number 16 * medium medium the secondnumber 18 * number 18 * medium the second the number 30 medium secondnumber 30 low number 32 Operation the first low the first the firstnumber 20 * low low the second number 20 * number high number the 20 *the 28 second second medium low number 30 number 32

Each column of Table I may identify operations with a same exponentrank. The leftmost column contains operations that result in the highestrank or that generate the most significant bits of the final output.Rightmost column contains operations with the lowest rank or the leastsignificant bits of the final output. The significance of the operationsincreases from the right column to the left column.

For example assume that, the first and second numbers 12, 26 arefloat32, and that the first high number 16, the first medium number 18,the first low number 20, the second high number 28, the second mediumnumber 30 and the second low number 32 are in Bfloat 16. Then, the “HighExponent” may be equal to the exponent of the first number 12 plus theexponent of the second number 26. The “Medium High Exponent” may be lessthan the exponent of the first number 12 minus 8 plus the exponent ofthe second number 26. The “Medium Exponent” may be less than theexponent of the first number 12 minus 16 plus the exponent of the secondnumber 26. The “Medium Low Exponent” may be less than the exponent ofthe first number 12 minus 16 plus the exponent of the second number 26minus 8. The “Low Exponent” may be less than the exponent of the firstnumber 12 minus 16, plus the exponent of the second number 26 minus 16.

To calculate a complete result, the contents of each column may beaccumulated to a common accumulator. For example, if the accumulator isa floating-point-style accumulator that contains exponent and signedmantissa (e.g., sign and magnitude) order of additions may be executedfrom lowest to highest rank or from the rightmost column to the leftmostcolumn. Doing so may allow accumulation from lower to higher mantissabits before truncations occur, for example during normalization of theresult.

In some embodiments, some of the operations (e.g., the rightmost columnoperations) may be omitted. For example, if an accumulator has smallamount of mantissa bits, some ranks may be skipped. For example, if theaccumulator is a float32 accumulator, skipping the two last ranks(Medium Low Exponent and Low Exponent operations) may produce negligibleerror increases.

Furthermore, in some embodiments some of the ranks may be skipped basedon performance metrics. For example, if the process 10 is associatedwith training process of a neural network, the process 10 may furtherconsider adjusting the used ranks based on whether the neural networkconverges towards a solution (e.g., produces reliably consistentresults). For example, to reduce the resources used, the process 10 maydetermine that only the High Exponent, the Medium High Exponent and theMedium Exponent rank operations are to be used to determine weights totrain the neural network. Therefore, the multiplication operation 22 mayonly calculate the result of the High Exponent, the Medium High Exponentand the Medium Exponent ranks. The medium low exponent and low exponentranks may not be calculated. Therefore, the multiplication execution 22may utilize less resources to generate the third number 34, at a cost toaccuracy and granularity.

The neural network may use the third number 34 for training. If theneural network does not converge towards a solution, then the process 10may be adjusted to include more ranks to calculate the third number 34(e.g., the medium low exponent rank and the low exponent rank).Therefore, the granularity and accuracy of the process 10 may beadjusted based on a performance metric (e.g., whether accurate outputsare being achieved).

In the alternative, if an accumulator has large amount of mantissa bitsan order of the operations may be important. For example, if theaccumulator is approximately the 256+log 2(num_of_addends), the numberof mantissa bits addition may become lossless.

Process 10 illustrates multiplication of two numbers 12, 26. In someembodiments, process 10 may be applied to a larger sized matrixmultiplication in which a plurality of matrix numbers is multipliedagainst a plurality of matrix numbers. For example, to multiply float32matrices of size 32×32 using Bfloat16 hardware units, each of the valuesmay be converted into three Bfloat16 values. This generates three 32×32Bfloat16-only matrices for each float32 matrix value. Those matrices maybe multiplied together as described in Table I above, with intermediateresults stored in accumulators. Final results may be converted to atarget precision (either float32 or bfloat).

Therefore, process 10 introduces a way for implementing multiplicationbased on various data types. For example, the resulting multiplication22 results in a third number 34 that may be in the second type of dataformat. As noted, the multiplication operation 22 accepts low-highnumbers 16, 18, 20, 28, 30, 32 that are in the first type of data formatto produce the third number 34 in the second type of data format.Moreover, the granularity of the process 10 may be adjusted on the flyto balance accuracy of the third number 34 against performance costs.

FIG. 2 shows a method 50 of executing multiplication. In an embodiment,the method 50 is implemented in one or more modules as a set of logicinstructions stored in a machine- or computer-readable storage mediumsuch as random access memory (RAM), read only memory (ROM), programmableROM (PROM), firmware, flash memory, etc., in configurable logic such as,for example, programmable logic arrays (PLAs), field programmable gatearrays (FPGAs), complex programmable logic devices (CPLDs), infixed-functionality logic hardware using circuit technology such as, forexample, application specific integrated circuit (ASIC), complementarymetal oxide semiconductor (CMOS) or transistor-transistor logic (TTL)technology, or any combination thereof.

For example, computer program code to carry out operations shown in themethod 50 may be written in any combination of one or more programminglanguages, including an object oriented programming language such asJAVA, SMALLTALK, C++ or the like and conventional procedural programminglanguages, such as the “C” programming language or similar programminglanguages. Additionally, logic instructions might include assemblerinstructions, instruction set architecture (ISA) instructions, machineinstructions, machine dependent instructions, microcode, state-settingdata, configuration data for integrated circuitry, state informationthat personalizes electronic circuitry and/or other structuralcomponents that are native to hardware (e.g., host processor, centralprocessing unit/CPU, microcontroller, etc.).

Illustrated processing block 52, in response to an identification thatone or more hardware units are to execute on a first type of dataformat, decomposes a first original floating point number to a pluralityof first segmented floating point numbers. The plurality of firstsegmented floating point numbers are to be equivalent to the firstoriginal floating point number. One or more of the first segmentedfloating point numbers has a first total number of bits that aredifferent than a second total number of bits of the first originalfloating point number.

Processing block 54, in response to the identification, decomposes asecond original floating point number to a plurality of second segmentedfloating point numbers. The second segmented floating point numbers areto be equivalent to the second original floating point number. One ormore of the second segmented floating point numbers has a third totalnumber of bits that are different than a fourth total number of bits ofthe second original floating point number.

Processing block 56 executes a multiplication operation on the first andsecond segmented floating point numbers to multiply the first segmentedfloating point numbers with the second segmented floating point numbers.For example, processing block 56 multiplies a subset of the plurality offirst segmented floating point numbers with a subset of the plurality ofsecond segmented floating point numbers to generate a plurality ofvalues. In some embodiments, processing block 56 includes executing amatrix multiplication operation that is to include an addition of theplurality of values together to generate a final output.

In some embodiments, the method 50 includes storing a summation of theplurality of values in a first accumulator and storing the final outputin a second accumulator. For example, a first value may be stored in thefirst accumulator, where the first value is a summation of only a subsetof the plurality of values. Furthermore, the final output is generatedby adding the first value, that is stored in the first accumulator, to asecond value stored in the second accumulator to generate the finaloutput.

FIG. 3A illustrates a process 300 to execute matrix multiplication. Indetail, a first matrix A 302 is multiplied with a second matrix B 304.The first matrix A 302 may composed of blocks A₀₀, A₀₁, A₀₂ . . .A_(0n). Each of blocks A₀₀, A₀₁, A₀₂ . . . A_(0n) may be of a seconddata format (e.g., FP32). Thus, the first matrix A 302 may beapproximately 32×(N*32). Likewise, the second matrix B 304 may becomposed of four blocks B₀₀, B₁₀, B₂₀, B_(n0) that are each of thesecond data format to be approximately (N*32)×32. Each of blocks A₀, A₁,A₂ . . . A_(n), B₀, B₁, B₂ . . . B_(n) may be decomposed to executematrix multiplication. For example, process 300 may decompose the matrixA 302 and the second matrix B 304 into smaller components 306. Forexample, for some applications of Generic Element Matrix Multiplication(GEMM) sizes, the input blocks A₀₀, A₀₁, A₀₂, A_(0n), B₀₀, B₁₀, B₂₀, Booare blocked into smaller components.

For example, the first matrix A 302 may be decomposed into a pluralityof components 310 and the second matrix B 304 may be decomposed into aplurality of components 308. Each of the components 310 may be of afirst data format (e.g., Bfloat16) that is different than the seconddata format. Block A₀₀ may be decomposed into three components includinga low component LA₀₀, a medium component MA₀₀ and a high component HA₀₀.For example, a sum of the low component LA₀₀, the medium component MA₀₀and the high component HAN may be approximately or precisely equal toA₀₀ of the first matrix A 302. In detail, the low component LA₀₀, themedium component MA₀₀ and a high component HAN may include correspondingportions of a mantissa of the block A₀₀ of the first matrix A 302 asdescribed above with FIG. 1. Likewise, each of the other blocks A₀₁, A₀₂. . . A_(0n) of the first matrix A 302 and blocks B₀, B₁, B₂ . . .B_(n0) of the second matrix B 304 may be decomposed into components 310,308 to each be approximately or precisely equal to sums of the smallercomponents. For example, the components 310, 308 may include lowcomponents LA₀₁-LA_(0n), LB₀₁-LB_(n0), medium components MA₀₁-MA_(0n),MB₀₀-MB_(n0) and high components HA₀₁-HA_(0n), HB₀₀-HB_(n0).

The process 300 may include execution of a matrix multiplicationoperation on the components 310, 308 generate a final output C 314. Inorder to compute final output C 314, several operations may be executed.An output of each operation is called a “Partial Product.” These PartialProducts may be accumulated to compute a final result. To maintain acertain level of accuracy and/or precision, an accumulator may need tobe of a sufficient size to ensure that relevant bits are not gettingdropped.

FIG. 3B illustrates a more detailed embodiment of the execution of thematrix multiplication 306 in which a single long accumulator P_(P00)(e.g., 256 bits) is employed. Operation One 320 may be the equivalent of_(A00)*_(BOO) of the matrices 302, 304. Operation One 320 may multiplylow component L_(A00) with low component L_(B00) and store the result inthe partial product accumulator P_(P00). P_(P00) may be normalized atthis time, and each time a new product is added to P_(P00). The mediumcomponents M_(A00) and L_(B00) may be multiplied together, added to thepartial product P_(P00) and then stored in the partial product P_(P00).Operation One 320 may proceed as described herein to multiply each ofthe low, mid and high components L_(A00), M_(A00), H_(A00) with each ofthe low, mid and high components L_(B00), M_(B00), H_(B00) and add theresulting products to the partial product accumulator P_(P00). Forexample, Operation One 320 may multiply H_(A00) and H_(B00) together,add the result of the product to the partial product accumulator P_(P00)and store the final result in the partial product accumulator P_(P00).

Operation Two 322 may then execute. Operation Two 322 may be theequivalent of A₀₁*B₁₀ of the matrices 302, 304. Operation Two 322 mayproceed as described herein to multiply each of the low, mid and highcomponents LA₀₁, MA₀₁, HA₀₁ with each of the low, mid and highcomponents LB₁₀, MB₁₀, HB₁₀ and add the resulting products to thepartial product accumulator PP₀₀. The execution of the matrixmultiplication 312 may then iterate similarly to as described above toexecute unillustrated operations to calculate the equivalence of A₀₂multiplied with B₂₀ and the remainder of the matrix multiplicationoperations until Operation N 324.

Operation N 324 be the equivalent of A_(0n)*B_(n0) of the matrices 302,304. Similarly to as described above, each of the low, mid and highcomponents LA_(0n), MA_(0n), HA_(0n) may be multiplied with each of thelow, mid and high components LB_(n0), MB_(n0), HB_(n0) with theresulting products being added to the partial product accumulator PP₀₀.The final calculation results in final product C.

As illustrated, each of the Operations One-N 320, 322, 324 processes inan order from the least significant numbers to the most significantnumbers to avoid truncation. For example, each of the Operations One320-Operations N 324 processes from the low components LA₀₀-LA_(0n),LB₀₀-LB_(n0) (e.g., the smallest numbers), to the medium componentsMA₀₀-MA_(0n), MB₀₀-MB_(n0) (e.g., the medium numbers) and lastly thehigh components HA₀₀-HA_(0n), HB₀₀-HB_(n0) (e.g., the largest numbers).

For example, Operation One 320 executes the multiplication of the lowcomponents LA₀₀ and LB₀₀ before the multiplication of the highcomponents HA₀₀ and HB₀₀. Doing so may reduce the possibility of losinglower order bits before normalization of the partial product accumulatorPP₀₀. That is, LA₀₀ and LB₀₀ may produce a significantly smaller productthan HA₀₀ and HB₀₀. Normalization (e.g., storing in scientific notationwith one non-zero decimal digit before the decimal point) may result intruncation of lower digits due to size constraints of the partialproduct accumulator PP₀₀.

FIG. 3C illustrates another more detailed embodiment of the execution ofthe matrix multiplication 312 in which two accumulators AP, MP areemployed instead of one accumulator. Master accumulator MP may be amaster accumulator of a smaller size (e.g., 32 bits). The activeaccumulator AP may be a smaller size as well (e.g., 38 bits) but largerthan the master accumulator MP. Having two smaller accumulators AP, MPmay be high precision and reduce an amount of required hardware and arearelative to employing one large accumulator.

Operation One 330 may be the equivalent of A₀₀*B₀₀ of the matrices 302,304. Operation One 330 may multiply low component LA₀₀ with lowcomponent LB₀₀ and store the result in the active accumulator AP. Theactive accumulator AP may be normalized at this time, and each time anew product is added to the active accumulator AP. The medium componentMA₀₀ and low component LB₀₀ may be multiplied together, added to theactive accumulator AP and then stored in the active accumulator AP.Operation One 330 may proceed as described herein to multiply each ofthe low, mid and high components LA₀₀, MA₀₀, HA₀₀ with each of the low,mid and high components LB₀₀, MB₀₀, HB₀₀ and add the resulting productsto the active accumulator AP. Lastly, Operation One 320 may multiplyHA₀₀ and HB₀₀ together, add the result of the product to the activeaccumulator AP and store the final result in the master accumulator MP.The active accumulator AP may also be reset to 0 before Operation Two332 executes.

Operation Two 332 may then execute. Operation Two 332 may be theequivalent of A₀₁*B₁₀ of the matrices 302, 304. Operation Two 332 mayproceed as described herein to multiply each of the low, mid and highcomponents LA₀₁, MA₀₁, HA₀₁ with each of the low, mid and highcomponents LB₁₀, MB₁₀, HB₁₀ and add the resulting products to the activeaccumulator AP. As illustrated, after processing of the highestcomponents HA₀₁ and HB₁₀, the active accumulator AP is added to themaster accumulator MP and stored in the master accumulator MP. Theactive accumulator AP may be reset to 0. The execution of the matrixmultiplication 312 may then iterate similarly to as described above toexecute unillustrated operations to calculate the equivalence theremainder of the matrix multiplication operations until Operation N 324.

Operation N 334 be the equivalent of A_(0n)*B_(n0) of the matrices 302,304. Similarly to as described above, each of the low, mid and highcomponents LA_(0n), MA_(0n), HA_(0n) may be multiplied with each of thelow, mid and high components LB_(n0), MB_(n0), HB_(n0) with theresulting products being added to the active accumulator AP. The activeaccumulator AP is eventually added to the master accumulator MP togenerate the final product C.

As illustrated, each of the Operations One-N 330, 332, 334 processes inan order from the least significant numbers to the most significantnumbers to avoid truncation. For example, each of the Operations One330-Operations N 334 processes from the low components LA₀₀-LA_(0n),LB₀₀-LB_(n0) (e.g., the smallest numbers), to the medium componentsMA₀₀-MA_(0n), MB₀₀-MB_(n0) (e.g., the medium numbers) and lastly thehigh components HA₀₀-HA_(0n), HB₀₀-HB_(n0) (e.g., the largest numbers).

For example, Operation One 330 executes the multiplication of the lowcomponents LA₀₀ and LB₀₀ before the multiplication of the highcomponents HAN) and HB₀₀. Doing so may reduce the possibility of losinglower order bits before normalization of the active accumulator AP. Thatis, multiplication of LA₀₀ and LB₀₀ may produce a significantly smallervalue than a value of the product of HA₀₀ and HB₀₀. Likewise, several ofthe other illustrated multiplications (e.g., MA₀₀×LB₀₀) may result insignificantly smaller values than the value of product of HA₀₀ and HB₀₀.Normalization (e.g., storing in scientific notation with one non-zerodecimal digit before the decimal point) may result in truncation ofsmaller values due to size constraints of the active accumulator AP. Asum of the smaller values however may be large enough to avoidtruncation. Thus, to avoid losing the cumulative sum of the smallervalues, HA₀₀ and HB₀₀ are processed last in Operation One 330.

As described above, both the embodiments described in FIGS. 3B and 3Cmay be adjusted based on performance metrics. For example, lowergranularity may be used to omit some lower component operations whileachieving certain performance metrics (e.g., converging towards asolution, achieve correct outcomes, processing within a certain timeperiod). Furthermore, the size of the matrices described above may beadjusted without affecting the applicability or application of theabove.

FIG. 4 shows a method 350 of adjusting a granularity of matrixmultiplication operations as described above with respect to theprocesses of 10 and 300. More particularly, the method 350 may beimplemented in one or more modules as a set of logic instructions storedin a machine- or computer-readable storage medium such as RAM, ROM,PROM, firmware, flash memory, etc., in configurable logic such as, forexample, PLAs, FPGAs, CPLDs, in fixed-functionality logic hardware usingcircuit technology such as, for example, ASIC, CMOS or TTL technology,or any combination thereof.

Processing block 352 receives neural network data. The neural networkdata may be matrices that each contain numbers. Processing block 356 maydecompose the neural network data into components. For example, thematrices may each be decomposed into low, middle and high components.Processing block 358 may identify a control variable that indicatesrelevant components. For example, the control variable may indicate agranularity of matrix multiplication operations. Processing block 360may execute matrix multiplication operations on a plurality of the low,middle and high components based on the control variable. For example,the control variable may indicate that only higher order components areto be processed during the matrix multiplication. Doing so may reduce atime and hardware cost of the matrix multiplication at a cost toaccuracy. In some other embodiments, the control variable may indicatethat all the low, middle and high components are to be processed duringthe matrix multiplication.

Processing block 362 determines whether the neural network convergestowards a solution. If not, processing block 364 adjusts the controlvariable to include more components. For example assume that the controlvariable originally indicated that only the high components were usedduring the matrix multiplication. The control variable may then beadjusted to include the high and middle components during future neuralnetwork processing.

If processing block 362 determines that the neural network convergestowards a solution, processing block 366 may determine whether to reducethe components based on one or more factors. For example, the one ormore factors may include whether a desired processing time is being met,whether a reduction in hardware usage is required, whether a previouslyunsuccessful reduction occurred in the past. For example, if the controlvariable currently indicates that the high and middle components are tobe processed, processing block 366 may determine whether the controlvariable was ever reduced to only include the high components in thepast, and whether the reduction resulted in convergence. If the controlvariable was successfully reduced in the past, processing block 368 mayadjust the control variable to reduce the components to include only thehigh components. If the control variable was not successfully reduced inthe past, processing block 370 may maintain the control variable withoutany adjustment. If there is no indication of whether a previousreduction was successful, processing block 368 may execute.

Thus, if processing block 366 determines that the components should notbe reduced, processing block 370 may maintain the control variablewithout any adjustment. If processing block 366 determines that thecomponents should be reduced, processing block 368 may adjust thecontrol variable to reduce the components.

FIG. 5 illustrates a process 500 to decompose a FP32 number to Bfloat16numbers. In detail, number 502 is an FP32 representation that includes amantissa that is approximately 23 bits (23 bits fraction). The mantissamay be the portions labeled with “F.” The number 502 may further includea sign bit (labeled as “S”) and 8 exponent bits labeled as “E.” Process504 may decompose the number 502 into Bfloat16 numbers 506, 508, 510similarly to as described above. Each of the numbers 506, 508, 510 maybe a Bfloat16 representation with the mantissa being approximately 7bits, a single sign bit, and 8 exponent bits. Thus, the FP32 number 502may naturally fit into the three Bfloat16 numbers 506, 508, 510. In someembodiments, the mantissas of the numbers 502, 506, 508, 510 may beincreased by a bit to include an implicit J-bit.

Turning now to FIG. 6, an efficiency-enhanced computing system 158 isshown. The computing system 158 may generally be part of an electronicdevice/platform having computing functionality (e.g., personal digitalassistant/PDA, notebook computer, tablet computer, convertible tablet,server), communications functionality (e.g., smart phone), imagingfunctionality (e.g., camera, camcorder), media playing functionality(e.g., smart television/TV), wearable functionality (e.g., watch,eyewear, headwear, footwear, jewelry), vehicular functionality (e.g.,car, truck, motorcycle), etc., or any combination thereof. In theillustrated example, the system 158 includes a host processor 160 (e.g.,CPU with one or more processor cores) having an integrated memorycontroller (IMC) 162 that is coupled to a system memory 164.

The illustrated system 158 also includes a graphics processor 168 (e.g.,graphics processing unit/GPU) and an input output (10) module 166implemented together with the processor 160 (e.g., as microcontrollers)on a semiconductor die 170 as a system on chip (SOC), where the IOmodule 166 may communicate with, for example, a display 172 (e.g., touchscreen, liquid crystal display/LCD, light emitting diode/LED display), anetwork controller 174 (e.g., wired and/or wireless), and mass storage176 (e.g., HDD, optical disc, SSD, flash memory or other NVM).

The illustrated SOC 170 includes a series of accelerators A0-A2. Theaccelerators A0-A2 may be configured to execute an operation on a firsttype of data format (e.g., Bfloat 16). The SOC 170 may further includelogic 120 with logic instructions, which when executed by the hostprocessor 160, cause the computing system 158 to perform one or moreaspects of the process 10 of FIG. 1, the method 50 of FIG. 2, theprocess 300 of FIG. 3A, the method 350 of FIG. 4, the process 500 ofFIG. 5, already discussed. In some embodiments, the system memory 164may include instructions, which when executed by the computing system158, cause the computing system 158 to perform one or more aspects ofthe process 10 of FIG. 1, the method 50 of FIG. 2, the process 300 ofFIG. 3A, the method 350 of FIG. 4, the process 500 of FIG. 5. The SOC170 may further include a first accumulator 122 (e.g., a hardwareregister) and a second accumulator 124 (e.g., a hardware register). Thefirst accumulator 122 may be a different size than the secondaccumulator 124. The first accumulator 122 may store temporary outputsassociated with the execution of the one or more aspects, while thesecond accumulator 124 may store a total output associated with theexecution of the one or more aspects.

Thus, the illustrated SOC 170 may decompose a first original floatingpoint number (e.g., a FP32 number) to a plurality of first segmentedfloating point numbers (e.g., Bfloat16 numbers). A sum of the firstsegmented floating point numbers may be equivalent to the first originalfloating point number. The SOC 170 may further decompose a secondoriginal floating point number (e.g., a FP32 number) to a plurality ofsecond segmented floating point numbers (e.g., Bfloat16 numbers). A sumof the plurality of second segmented floating point numbers may beequivalent to the second original floating point number. The SOC 170 mayuse the accelerators A0-A2 to execute a multiplication operation on thefirst and second segmented floating point numbers to multiply the firstsegmented floating point numbers with the second segmented floatingpoint numbers, and store outputs in the first accumulator 122 and thesecond accumulator 124.

Accordingly, the computing system 100 may be considered to be efficiencyenhanced in that the computing system 100 may utilize existing hardware,such as accelerators A0-A2, to execute operations on different types ofdata formats. Therefore, specialized hardware for each type of dataformat may not be needed, thereby reducing the size of SOC 170 whileincreasing the flexibility and functionality of the SOC 170. Moreover,the usage of first and second accumulators 122, 124 may reduce the spaceneeded for the SOC 170. For example, if the first and secondaccumulators 122, 124 were replaced by one large accumulator, a size ofthe one large accumulator would be far larger than a combined size ofthe first and second accumulators 122, 124.

FIG. 7 shows a semiconductor package apparatus 180. The illustratedapparatus 180 includes one or more substrates 184 (e.g., silicon,sapphire, gallium arsenide) and logic 182 (e.g., transistor array andother integrated circuit/IC components) coupled to the substrate(s) 184.In one example, the logic 182 is implemented at least partly inconfigurable logic or fixed-functionality logic hardware. The logic 182may implement one or more aspects of the process 10 of FIG. 1, themethod 50 of FIG. 2, The process 300 of FIG. 3A, the method 350 of FIG.4, the process 500 of FIG. 5, already discussed. In one example, thelogic 182 includes transistor channel regions that are positioned (e.g.,embedded) within the substrate(s) 184. Thus, the interface between thelogic 182 and the substrate(s) 184 may not be an abrupt junction. Thelogic 182 may also be considered to include an epitaxial layer that isgrown on an initial wafer of the substrate(s) 184.

FIG. 8 illustrates a processor core 200 according to one embodiment. Theprocessor core 200 may be the core for any type of processor, such as amicro-processor, an embedded processor, a digital signal processor(DSP), a network processor, or other device to execute code. Althoughonly one processor core 200 is illustrated in FIG. 8, a processingelement may alternatively include more than one of the processor core200 illustrated in FIG. 8. The processor core 200 may be asingle-threaded core or, for at least one embodiment, the processor core200 may be multithreaded in that it may include more than one hardwarethread context (or “logical processor”) per core.

FIG. 8 also illustrates a memory 270 coupled to the processor core 200.The memory 270 may be any of a wide variety of memories (includingvarious layers of memory hierarchy) as are known or otherwise availableto those of skill in the art. The memory 270 may include one or morecode 213 instruction(s) to be executed by the processor core 200,wherein the code 213 may implement the process 10 of FIG. 1, the method50 of FIG. 2, The process 300 of FIG. 3A, the method 350 of FIG. 4, theprocess 500 of FIG. 5, already discussed. The processor core 200 followsa program sequence of instructions indicated by the code 213. Eachinstruction may enter a front end portion 210 and be processed by one ormore decoders 220. The decoder 220 may generate as its output a microoperation such as a fixed width micro operation in a predefined format,or may generate other instructions, microinstructions, or controlsignals which reflect the original code instruction. The illustratedfront end portion 210 also includes register renaming logic 225 andscheduling logic 230, which generally allocate resources and queue theoperation corresponding to the convert instruction for execution.

The processor core 200 is shown including execution logic 250 having aset of execution units 255-1 through 255-N. Some embodiments may includea number of execution units dedicated to specific functions or sets offunctions. Other embodiments may include only one execution unit or oneexecution unit that can perform a particular function. The illustratedexecution logic 250 performs the operations specified by codeinstructions.

After completion of execution of the operations specified by the codeinstructions, back end logic 260 retires the instructions of the code213. In one embodiment, the processor core 200 allows out of orderexecution but requires in order retirement of instructions. Retirementlogic 265 may take a variety of forms as known to those of skill in theart (e.g., re-order buffers or the like). In this manner, the processorcore 200 is transformed during execution of the code 213, at least interms of the output generated by the decoder, the hardware registers andtables utilized by the register renaming logic 225, and any registers(not shown) modified by the execution logic 250.

Although not illustrated in FIG. 8, a processing element may includeother elements on chip with the processor core 200. For example, aprocessing element may include memory control logic along with theprocessor core 200. The processing element may include I/O control logicand/or may include I/O control logic integrated with memory controllogic. The processing element may also include one or more caches.

Referring now to FIG. 9, shown is a block diagram of a computing system1000 embodiment in accordance with an embodiment. Shown in FIG. 9 is amultiprocessor system 1000 that includes a first processing element 1070and a second processing element 1080. While two processing elements 1070and 1080 are shown, it is to be understood that an embodiment of thesystem 1000 may also include only one such processing element.

The system 1000 is illustrated as a point-to-point interconnect system,wherein the first processing element 1070 and the second processingelement 1080 are coupled via a point-to-point interconnect 1050. Itshould be understood that any or all of the interconnects illustrated inFIG. 9 may be implemented as a multi-drop bus rather than point-to-pointinterconnect.

As shown in FIG. 9, each of processing elements 1070 and 1080 may bemulticore processors, including first and second processor cores (i.e.,processor cores 1074 a and 1074 b and processor cores 1084 a and 1084b). Such cores 1074 a, 1074 b, 1084 a, 1084 b may be configured toexecute instruction code in a manner similar to that discussed above inconnection with FIG. 6.

Each processing element 1070, 1080 may include at least one shared cache1896 a, 1896 b. The shared cache 1896 a, 1896 b may store data (e.g.,instructions) that are utilized by one or more components of theprocessor, such as the cores 1074 a, 1074 b and 1084 a, 1084 b,respectively. For example, the shared cache 1896 a, 1896 b may locallycache data stored in a memory 1032, 1034 for faster access by componentsof the processor. In one or more embodiments, the shared cache 1896 a,1896 b may include one or more mid-level caches, such as level 2 (L2),level 3 (L3), level 4 (L4), or other levels of cache, a last level cache(LLC), and/or combinations thereof.

While shown with only two processing elements 1070, 1080, it is to beunderstood that the scope of the embodiments are not so limited. Inother embodiments, one or more additional processing elements may bepresent in a given processor. Alternatively, one or more of processingelements 1070, 1080 may be an element other than a processor, such as anaccelerator or a field programmable gate array. For example, additionalprocessing element(s) may include additional processors(s) that are thesame as a first processor 1070, additional processor(s) that areheterogeneous or asymmetric to processor a first processor 1070,accelerators (such as, e.g., graphics accelerators or digital signalprocessing (DSP) units), field programmable gate arrays, or any otherprocessing element. There can be a variety of differences between theprocessing elements 1070, 1080 in terms of a spectrum of metrics ofmerit including architectural, micro architectural, thermal, powerconsumption characteristics, and the like. These differences mayeffectively manifest themselves as asymmetry and heterogeneity amongstthe processing elements 1070, 1080. For at least one embodiment, thevarious processing elements 1070, 1080 may reside in the same diepackage.

The first processing element 1070 may further include memory controllerlogic (MC) 1072 and point-to-point (P-P) interfaces 1076 and 1078.Similarly, the second processing element 1080 may include a MC 1082 andP-P interfaces 1086 and 1088. As shown in FIG. 9, MC's 1072 and 1082couple the processors to respective memories, namely a memory 1032 and amemory 1034, which may be portions of main memory locally attached tothe respective processors. While the MC 1072 and 1082 is illustrated asintegrated into the processing elements 1070, 1080, for alternativeembodiments the MC logic may be discrete logic outside the processingelements 1070, 1080 rather than integrated therein.

The first processing element 1070 and the second processing element 1080may be coupled to an I/O subsystem 1090 via P-P interconnects 1076 1086,respectively. As shown in FIG. 9, the I/O subsystem 1090 includes P-Pinterfaces 1094 and 1098. Furthermore, I/O subsystem 1090 includes aninterface 1092 to couple I/O subsystem 1090 with a high performancegraphics engine 1038. In one embodiment, bus 1049 may be used to couplethe graphics engine 1038 to the I/O subsystem 1090. Alternately, apoint-to-point interconnect may couple these components.

In turn, I/O subsystem 1090 may be coupled to a first bus 1016 via aninterface 1096. In one embodiment, the first bus 1016 may be aPeripheral Component Interconnect (PCI) bus, or a bus such as a PCIExpress bus or another third generation I/O interconnect bus, althoughthe scope of the embodiments are not so limited.

As shown in FIG. 9, various I/O devices 1014 (e.g., biometric scanners,speakers, cameras, sensors) may be coupled to the first bus 1016, alongwith a bus bridge 1018 which may couple the first bus 1016 to a secondbus 1020. In one embodiment, the second bus 1020 may be a low pin count(LPC) bus. Various devices may be coupled to the second bus 1020including, for example, a keyboard/mouse 1012, communication device(s)1026, and a data storage unit 1019 such as a disk drive or other massstorage device which may include code 1030, in one embodiment. Theillustrated code 1030 may implement the process 10 of FIG. 1, the method50 of FIG. 2, The process 300 of FIG. 3A, the method 350 of FIG. 4, theprocess 500 of FIG. 5, already discussed. Further, an audio I/O 1024 maybe coupled to second bus 1020 and a battery 1010 may supply power to thecomputing system 1000.

Note that other embodiments are contemplated. For example, instead ofthe point-to-point architecture of FIG. 9, a system may implement amulti-drop bus or another such communication topology. Also, theelements of FIG. 9 may alternatively be partitioned using more or fewerintegrated chips than shown in FIG. 9.

ADDITIONAL NOTES AND EXAMPLES

Example 1 may include a computing system comprising a host processorthat are to execute on a first data format, the host processor includinga plurality of accelerators, and a memory coupled to the host processor,the memory including executable program instructions, which whenexecuted by the host processor, cause the computing system to inresponse to an identification that the accelerators execute on the firsttype of data format, decompose a first original floating point number toa plurality of first segmented floating point numbers that are to beequivalent to the first original floating point number, in response tothe identification, decompose a second original floating point number toa plurality of second segmented floating point numbers that are to beequivalent to the second original floating point number, and execute, byone or more of the plurality of accelerators, a multiplication operationon the first and second segmented floating point numbers to multiply thefirst segmented floating point numbers with the second segmentedfloating point numbers.

Example 2 may include the computing system of Example 1, wherein theexecutable program instructions, when executed by the computing system,cause the computing system to execute the multiplication operation tomultiply a subset of the plurality of first segmented floating pointnumbers with a subset of the plurality of second segmented floatingpoint numbers to generate a plurality of values

Example 3 may include the computing system of Example 2, wherein theexecutable program instructions, when executed by the computing system,cause the computing system to execute a matrix multiplication operationthat is to include an addition of the plurality of values together togenerate a final output.

Example 4 may include the computing system of Example 3, wherein theexecutable program instructions, when executed by the computing system,cause the computing system to store a summation of the plurality ofvalues in a first accumulator, and store the final output in a secondaccumulator.

Example 5 may include the computing system of Example 4, wherein theexecutable program instructions, when executed by the computing system,cause the computing system to store a first value in the firstaccumulator, wherein the first value is a summation of only a subset ofthe plurality of values, and add the first value, that is stored in thefirst accumulator, to a second value stored in the second accumulator togenerate the final output.

Example 6 may include the computing system of any one of the Examples 1to 5, wherein the executable program instructions, when executed by thecomputing system, cause the computing system to generate one or more ofthe first segmented floating point numbers to have a first total numberof bits that are different than a second total number of bits of thefirst original floating point number, and generate one or more of thesecond segmented floating point numbers to have a third total number ofbits that are different than a fourth total number of bits of the secondoriginal floating point number.

Example 7 may include a semiconductor apparatus comprising one or moresubstrates, and logic coupled to the one or more substrates, wherein thelogic is implemented in one or more of configurable logic orfixed-functionality logic hardware, the logic coupled to the one or moresubstrates to in response to an identification that one or more hardwareunits are to execute on a first type of data format, decompose a firstoriginal floating point number to a plurality of first segmentedfloating point numbers that are to be equivalent to the first originalfloating point number, in response to the identification, decompose asecond original floating point number to a plurality of second segmentedfloating point numbers that are to be equivalent to the second originalfloating point number, and execute a multiplication operation on thefirst and second segmented floating point numbers to multiply the firstsegmented floating point numbers with the second segmented floatingpoint numbers.

Example 8 may include the apparatus of Example 7, wherein the logiccoupled to the one or more substrates is to execute the multiplicationoperation to multiply a subset of the plurality of first segmentedfloating point numbers with a subset of the plurality of secondsegmented floating point numbers to generate a plurality of values.

Example 9 may include the apparatus of Example 8, wherein the logiccoupled to the one or more substrates is to execute a matrixmultiplication operation that is to include an addition of the pluralityof values together to generate a final output.

Example 10 may include the apparatus of Example 9, wherein the logiccoupled to the one or more substrates is to store a summation of theplurality of values in a first accumulator, and store the final outputin a second accumulator.

Example 11 may include the apparatus of Example 10, wherein the logiccoupled to the one or more substrates is to store a first value in thefirst accumulator, wherein the first value is a summation of only asubset of the plurality of values, and add the first value, that isstored in the first accumulator, to a second value stored in the secondaccumulator to generate the final output.

Example 12 may include the apparatus of any one of Examples 7 to 11,wherein the logic coupled to the one or more substrates is to generateone or more of the first segmented floating point numbers to have afirst total number of bits that are different than a second total numberof bits of the first original floating point number, and generate one ormore of the second segmented floating point numbers to have a thirdtotal number of bits that are different than a fourth total number ofbits of the second original floating point number.

Example 13 may include the apparatus of Example 7, wherein the logiccoupled to the one or more substrates includes transistor channelregions that are positioned within the one or more substrates.

Example 14 may include at least one computer readable storage mediumcomprising a set of instructions, which when executed by a computingdevice, cause the computing device to in response to an identificationthat one or more hardware units are to execute on a first type of dataformat, decompose a first original floating point number to a pluralityof first segmented floating point numbers that are to be equivalent tothe first original floating point number, in response to theidentification, decompose a second original floating point number to aplurality of second segmented floating point numbers that are to beequivalent to the second original floating point number, and execute amultiplication operation on the first and second segmented floatingpoint numbers to multiply the first segmented floating point numberswith the second segmented floating point numbers.

Example 15 may include the at least one computer readable storage mediumof Example 14, wherein the instructions, when executed, cause thecomputing device to execute the multiplication operation to multiply asubset of the plurality of first segmented floating point numbers with asubset of the plurality of second segmented floating point numbers togenerate a plurality of values.

Example 16 may include the at least one computer readable storage mediumof Example 15, wherein the instructions, when executed, cause thecomputing device to execute a matrix multiplication operation that is toinclude an addition of the plurality of values together to generate afinal output.

Example 17 may include the at least one computer readable storage mediumof Example 16, wherein the instructions, when executed, cause thecomputing device to store a summation of the plurality of values in afirst accumulator, and store the final output in a second accumulator.

Example 18 may include the at least one computer readable storage mediumof Example 17, wherein the instructions, when executed, cause thecomputing device to store a first value in the first accumulator,wherein the first value is a summation of only a subset of the pluralityof values, and add the first value, that is stored in the firstaccumulator, to a second value stored in the second accumulator togenerate the final output.

Example 19 may include the at least one computer readable storage mediumof any one of Examples 14 to 18, wherein the instructions, whenexecuted, cause the computing device to generate one or more of thefirst segmented floating point numbers to have a first total number ofbits that are different than a second total number of bits of the firstoriginal floating point number, and generate one or more of the secondsegmented floating point numbers to have a third total number of bitsthat are different than a fourth total number of bits of the secondoriginal floating point number.

Example 20 may include a method comprising in response to anidentification that one or more hardware units are to execute on a firsttype of data format, decomposing a first original floating point numberto a plurality of first segmented floating point numbers that are to beequivalent to the first original floating point number, in response tothe identification, decomposing a second original floating point numberto a plurality of second segmented floating point numbers that are to beequivalent to the second original floating point number, and executing amultiplication operation on the first and second segmented floatingpoint numbers to multiply the first segmented floating point numberswith the second segmented floating point numbers.

Example 21 may include the method of Example 20, further comprisingexecuting the multiplication operation to multiply a subset of theplurality of first segmented floating point numbers with a subset of theplurality of second segmented floating point numbers to generate aplurality of values.

Example 22 may include the method of Example 21, further comprisingexecuting a matrix multiplication operation that is to include anaddition of the plurality of values together to generate a final output.

Example 23 may include the method of Example 22, further comprisingstoring a summation of the plurality of values in a first accumulator,and storing the final output in a second accumulator.

Example 24 may include the method of Example 23, further comprisingstoring a first value in the first accumulator, wherein the first valueis a summation of only a subset of the plurality of values, and addingthe first value, that is stored in the first accumulator, to a secondvalue stored in the second accumulator to generate the final output.

Example 25 may include the method of any one of Examples 20 to 24,further comprising generating one or more of the first segmentedfloating point numbers to have a first total number of bits that aredifferent than a second total number of bits of the first originalfloating point number, and generating one or more of the secondsegmented floating point numbers to have a third total number of bitsthat are different than a fourth total number of bits of the secondoriginal floating point number.

Thus, technology described herein may support an enhanced architectureto support complex matrix multiplication on existing hardware. Thetechnology may also enable a dynamically scalable architecture thatadjusts granularity of matrix multiplication operations on-the-fly toreduce hardware usage while achieving a desirable outcome.

Embodiments are applicable for use with all types of semiconductorintegrated circuit (“IC”) chips. Examples of these IC chips include butare not limited to processors, controllers, chipset components,programmable logic arrays (PLAs), memory chips, network chips, systemson chip (SOCs), SSD/NAND controller ASICs, and the like. In addition, insome of the drawings, signal conductor lines are represented with lines.Some may be different, to indicate more constituent signal paths, have anumber label, to indicate a number of constituent signal paths, and/orhave arrows at one or more ends, to indicate primary information flowdirection. This, however, should not be construed in a limiting manner.Rather, such added detail may be used in connection with one or moreexemplary embodiments to facilitate easier understanding of a circuit.Any represented signal lines, whether or not having additionalinformation, may actually comprise one or more signals that may travelin multiple directions and may be implemented with any suitable type ofsignal scheme, e.g., digital or analog lines implemented withdifferential pairs, optical fiber lines, and/or single-ended lines.

Example sizes/models/values/ranges may have been given, althoughembodiments are not limited to the same. As manufacturing techniques(e.g., photolithography) mature over time, it is expected that devicesof smaller size could be manufactured. In addition, well knownpower/ground connections to IC chips and other components may or may notbe shown within the figures, for simplicity of illustration anddiscussion, and so as not to obscure certain aspects of the embodiments.Further, arrangements may be shown in block diagram form in order toavoid obscuring embodiments, and also in view of the fact that specificswith respect to implementation of such block diagram arrangements arehighly dependent upon the computing system within which the embodimentis to be implemented, i.e., such specifics should be well within purviewof one skilled in the art. Where specific details (e.g., circuits) areset forth in order to describe example embodiments, it should beapparent to one skilled in the art that embodiments can be practicedwithout, or with variation of, these specific details. The descriptionis thus to be regarded as illustrative instead of limiting.

The term “coupled” may be used herein to refer to any type ofrelationship, direct or indirect, between the components in question,and may apply to electrical, mechanical, fluid, optical,electromagnetic, electromechanical or other connections. In addition,the terms “first”, “second”, etc. may be used herein only to facilitatediscussion, and carry no particular temporal or chronologicalsignificance unless otherwise indicated.

As used in this application and in the claims, a list of items joined bythe term “one or more of” may mean any combination of the listed terms.For example, the phrases “one or more of A, B or C” may mean A; B; C; Aand B; A and C; B and C; or A, B and C.

Those skilled in the art will appreciate from the foregoing descriptionthat the broad techniques of the embodiments can be implemented in avariety of forms. Therefore, while the embodiments have been describedin connection with particular examples thereof, the true scope of theembodiments should not be so limited since other modifications willbecome apparent to the skilled practitioner upon a study of thedrawings, specification, and following claims.

We claim:
 1. A computing system comprising: a host processor, the hostprocessor including a plurality of accelerators that are to execute on afirst data format; and a memory coupled to the host processor, thememory including executable program instructions, which when executed bythe host processor, cause the computing system to: in response to anidentification that the accelerators execute on the first type of dataformat, decompose a first original floating point number to a pluralityof first segmented floating point numbers that are to be equivalent tothe first original floating point number; in response to theidentification, decompose a second original floating point number to aplurality of second segmented floating point numbers that are to beequivalent to the second original floating point number; and execute, byone or more of the plurality of accelerators, a multiplication operationon the first and second segmented floating point numbers to multiply thefirst segmented floating point numbers with the second segmentedfloating point numbers.
 2. The computing system of claim 1, wherein theexecutable program instructions, when executed by the computing system,cause the computing system to execute the multiplication operation tomultiply a subset of the plurality of first segmented floating pointnumbers with a subset of the plurality of second segmented floatingpoint numbers to generate a plurality of values
 3. The computing systemof claim 2, wherein the executable program instructions, when executedby the computing system, cause the computing system to execute a matrixmultiplication operation that is to include an addition of the pluralityof values together to generate a final output.
 4. The computing systemof claim 3, wherein the executable program instructions, when executedby the computing system, cause the computing system to: store asummation of the plurality of values in a first accumulator; and storethe final output in a second accumulator.
 5. The computing system ofclaim 4, wherein the executable program instructions, when executed bythe computing system, cause the computing system to: store a first valuein the first accumulator, wherein the first value is a summation of onlya subset of the plurality of values; and add the first value, that isstored in the first accumulator, to a second value stored in the secondaccumulator to generate the final output.
 6. The computing system ofclaim 1, wherein the executable program instructions, when executed bythe computing system, cause the computing system to: generate one ormore of the first segmented floating point numbers to have a first totalnumber of bits that are different than a second total number of bits ofthe first original floating point number; and generate one or more ofthe second segmented floating point numbers to have a third total numberof bits that are different than a fourth total number of bits of thesecond original floating point number.
 7. A semiconductor apparatuscomprising: one or more substrates; and logic coupled to the one or moresubstrates, wherein the logic is implemented in one or more ofconfigurable logic or fixed-functionality logic hardware, the logiccoupled to the one or more substrates to: in response to anidentification that one or more hardware units are to execute on a firsttype of data format, decompose a first original floating point number toa plurality of first segmented floating point numbers that are to beequivalent to the first original floating point number; in response tothe identification, decompose a second original floating point number toa plurality of second segmented floating point numbers that are to beequivalent to the second original floating point number; and execute amultiplication operation on the first and second segmented floatingpoint numbers to multiply the first segmented floating point numberswith the second segmented floating point numbers.
 8. The apparatus ofclaim 7, wherein the logic coupled to the one or more substrates is toexecute the multiplication operation to multiply a subset of theplurality of first segmented floating point numbers with a subset of theplurality of second segmented floating point numbers to generate aplurality of values.
 9. The apparatus of claim 8, wherein the logiccoupled to the one or more substrates is to execute a matrixmultiplication operation that is to include an addition of the pluralityof values together to generate a final output.
 10. The apparatus ofclaim 9, wherein the logic coupled to the one or more substrates is to:store a summation of the plurality of values in a first accumulator; andstore the final output in a second accumulator.
 11. The apparatus ofclaim 10, wherein the logic coupled to the one or more substrates is to:store a first value in the first accumulator, wherein the first value isa summation of only a subset of the plurality of values; and add thefirst value, that is stored in the first accumulator, to a second valuestored in the second accumulator to generate the final output.
 12. Theapparatus of claim 7, wherein the logic coupled to the one or moresubstrates is to: generate one or more of the first segmented floatingpoint numbers to have a first total number of bits that are differentthan a second total number of bits of the first original floating pointnumber; and generate one or more of the second segmented floating pointnumbers to have a third total number of bits that are different than afourth total number of bits of the second original floating pointnumber.
 13. The apparatus of claim 7, wherein the logic coupled to theone or more substrates includes transistor channel regions that arepositioned within the one or more substrates.
 14. At least one computerreadable storage medium comprising a set of instructions, which whenexecuted by a computing device, cause the computing device to: inresponse to an identification that one or more hardware units are toexecute on a first type of data format, decompose a first originalfloating point number to a plurality of first segmented floating pointnumbers that are to be equivalent to the first original floating pointnumber; in response to the identification, decompose a second originalfloating point number to a plurality of second segmented floating pointnumbers that are to be equivalent to the second original floating pointnumber; and execute a multiplication operation on the first and secondsegmented floating point numbers to multiply the first segmentedfloating point numbers with the second segmented floating point numbers.15. The at least one computer readable storage medium of claim 14,wherein the instructions, when executed, cause the computing device toexecute the multiplication operation to multiply a subset of theplurality of first segmented floating point numbers with a subset of theplurality of second segmented floating point numbers to generate aplurality of values.
 16. The at least one computer readable storagemedium of claim 15, wherein the instructions, when executed, cause thecomputing device to execute a matrix multiplication operation that is toinclude an addition of the plurality of values together to generate afinal output.
 17. The at least one computer readable storage medium ofclaim 16, wherein the instructions, when executed, cause the computingdevice to: store a summation of the plurality of values in a firstaccumulator; and store the final output in a second accumulator.
 18. Theat least one computer readable storage medium of claim 17, wherein theinstructions, when executed, cause the computing device to: store afirst value in the first accumulator, wherein the first value is asummation of only a subset of the plurality of values; and add the firstvalue, that is stored in the first accumulator, to a second value storedin the second accumulator to generate the final output.
 19. The at leastone computer readable storage medium of claim 14, wherein theinstructions, when executed, cause the computing device to: generate oneor more of the first segmented floating point numbers to have a firsttotal number of bits that are different than a second total number ofbits of the first original floating point number; and generate one ormore of the second segmented floating point numbers to have a thirdtotal number of bits that are different than a fourth total number ofbits of the second original floating point number.
 20. A methodcomprising: in response to an identification that one or more hardwareunits are to execute on a first type of data format, decomposing a firstoriginal floating point number to a plurality of first segmentedfloating point numbers that are to be equivalent to the first originalfloating point number; in response to the identification, decomposing asecond original floating point number to a plurality of second segmentedfloating point numbers that are to be equivalent to the second originalfloating point number; and executing a multiplication operation on thefirst and second segmented floating point numbers to multiply the firstsegmented floating point numbers with the second segmented floatingpoint numbers.
 21. The method of claim 20, further comprising executingthe multiplication operation to multiply a subset of the plurality offirst segmented floating point numbers with a subset of the plurality ofsecond segmented floating point numbers to generate a plurality ofvalues.
 22. The method of claim 21, further comprising executing amatrix multiplication operation that is to include an addition of theplurality of values together to generate a final output.
 23. The methodof claim 22, further comprising: storing a summation of the plurality ofvalues in a first accumulator; and storing the final output in a secondaccumulator.
 24. The method of claim 23, further comprising: storing afirst value in the first accumulator, wherein the first value is asummation of only a subset of the plurality of values; and adding thefirst value, that is stored in the first accumulator, to a second valuestored in the second accumulator to generate the final output.
 25. Themethod of claim 20, further comprising: generating one or more of thefirst segmented floating point numbers to have a first total number ofbits that are different than a second total number of bits of the firstoriginal floating point number; and generating one or more of the secondsegmented floating point numbers to have a third total number of bitsthat are different than a fourth total number of bits of the secondoriginal floating point number.